Definition of the Saturation Voltage
Using the EKV Model (Version 1)
Abstract
This notebook presents different definitions of the saturation voltage of a MOS transistor that is valid in all modes of inversion, from weak to strong inversion. It then ends with a simple approximation of the normalized drain-to-source saturation voltage that can be used for design.
Licensing
This document is licensed under the Creative Commons License CC BY-NC-SA 
1 Introduction
This notebook presents different definitions of the saturation voltage of a MOS transistor that is valid in all modes of inversion, from weak to strong inversion. It then ends with a simple approximation of the normalized drain-to-source saturation voltage that can be used for design.
2 Definition of the saturation voltage
The saturation voltage is the drain-to-source voltage \(V_{DS}\) above which the drain current saturates to the foward current \(I_F\) [1]. In strong inversion, the saturation voltage corresponds to the pinch-off voltage \(V_P\) and hence the drain-to-source saturation voltage is given by \(V_{DSsat} = V_P-V_S\) [1]. In weak inversion, we cannot defined a drain-to-source saturation voltage because the drain current tends asymptotically to \(I_F\). We cannot use \(V_P-V_S\) because it becomes zero in moderate inversion or negative in weak inversion. In order to try defining a saturation voltage in weak inversion, we rewrite the drain current in weak inversion as [1] \[\begin{equation} I_D = I_F \, \left[1-e^{-\frac{V_{DS}}{U_T}}\right] \end{equation}\] The relative error between the actual drain current \(I_D\) and the asymptotic value \(I_F\) is defined as [1] \[\begin{equation} \varepsilon \triangleq \left|\frac{I_D-I_F}{I_F}\right| = e^{-\frac{V_{DS}}{U_T}} = e^{-v_{ds}}. \end{equation}\] The relative error \(\varepsilon\) decreases exponentially with \(v_{ds} = V_{DS}/U_T\). The saturation voltage in weak inversion can be defined as the drain-to-source voltage for a given error \(\varepsilon\). Taking a saturation voltage of 4 \(U_T\), corresponding to \(V_{DSsat} =\) 103 \(mV\) at room temperature (\(T =\) 26.9 \(^\circ C\)), gives and error \(\varepsilon =\) 1.832 \(\%\).
The drain current can unfortunately not be expressed directly in term of the \(V_{DS}\) voltage. However, we can express the voltages versus the forward and reverse currents. Indeed, the voltages are related to the normalized charges at the source and drain according to [1] [2] [3] \[\begin{align} v_p-v_s &= \ln(q_s)+2 q_s,\label{eqn:vp_vs_qs}\\ v_p-v_d &= \ln(q_d)+2 q_d.\label{eqn:vp_vd_qd} \end{align}\] From \(\eqref{eqn:vp_vs_qs}\) and \(\eqref{eqn:vp_vd_qd}\) we can express the normalized drain-to-source voltage \(v_{ds}\) as a function of the normalized charges at the source \(q_s\) and drain \(q_d\) as \[\begin{equation}\label{eqn:vds_qs_qd} v_{ds} = v_d-v_s = 2(q_s-q_d) + \ln\left(\frac{q_s}{q_d}\right). \end{equation}\] Recalling that the normalized charges depend on the normalized forward and reverse currents according to \[\begin{align} q_s &= \frac{\sqrt{4 i_f+1}-1}{2},\\ q_d &= \frac{\sqrt{4 i_r+1}-1}{2}, \end{align}\] we can express \(v_{ds}\) in terms of \(i_f\) and \(i_r\). We can plot \(i_d/i_f=(i_f-i_r)/i_f\) versus the \(v_{ds}\) voltage in Figure 1 for different inversion coefficient \(IC\).
Figure 1 illustrates how the saturation voltage decreases as we move progressively from strong inversion to moderate and weak inversion.
We can rewrite \(\eqref{eqn:vds_qs_qd}\) in terms of the \(q_d/q_s\) ratio as \[\begin{equation}\label{eqn:vds_qs_over_qd} v_{ds} = 2 q_s\,\left(1-\frac{q_d}{q_s}\right) - \ln\left(\frac{q_d}{q_s}\right). \end{equation}\] Equation \(\eqref{eqn:vds_qs_over_qd}\) is plotted in Figure 2 for different values of \(IC\) and hence for different \(q_s\). We see that for \(q_d/q_s=1\) we are in the linear region and \(v_{ds}=0\). Decreasing the \(q_d/q_s\) ratio moves the operating point from the linear region into the saturation region increasing the \(v_{ds}\) voltage.
We could therefore also use the \(q_d/q_s\) ratio (or its inverse the \(q_s/q_d\) ratio) as a criterium to define the saturation voltage \[\begin{equation}\label{eqn:vdssat_r} v_{dssat} = 2 q_s\,(1-r)-\ln(r), \end{equation}\] where \(r=q_d/q_s\) and \(q_s\) depends on the inversion coefficient according to \[\begin{equation} q_s = \frac{\sqrt{4 IC+1}-1}{2}. \end{equation}\] Equation \(\eqref{eqn:vdssat_r}\) is plotted version the inversion coefficient in Figure 7 for various values of \(r = q_d/q_s\).
From Figure 3, we see that \(v_{ds}\) saturates in weak inversion to \(v_{ds,wi} \cong -\ln(r)\). The \(4 U_T\) value that is typically used corresponds to the curve for \(r =\) 1.832e-02.
In strong inversion the curve for \(r\ll 1\) tends asymptotically to the value of \(v_{dssat} \cong 2 q_s \cong v_p-v_s\).
The meaning of the \(r = q_d/q_s\) ratio might not be very intuitive at first glance and circuit designers prefer to express the saturation voltage in terms of the current ratio \(\alpha \triangleq I_R/I_F = i_r/i_f\) [4] [5] \[\begin{equation}\label{eqn:vdssat_alpha} v_{dssat} = \left(\sqrt{4\,i_f+1}-1\right)\,\left(1-\frac{\sqrt{4\,\alpha\,i_f+1}-1}{\sqrt{4\,i_f+1}-1}\right) - \ln\left(\frac{\sqrt{4\,\alpha\,i_f+1}-1}{\sqrt{4\,i_f+1}-1}\right). \end{equation}\] Assuming that \(\alpha =i_r/i_f < 1\), the forward current is simply equal to the inversion coefficient \(i_f = IC\). Equation \(\eqref{eqn:vdssat_alpha}\) is plotted versus \(IC\) in Figure 4 for different values of \(\alpha\).
\(v_{dssat}\) in weak inversion tends to \[\begin{equation} v_{dssat,wi} = - \ln\left(\frac{\sqrt{4\,\alpha\,i_f+1}-1}{\sqrt{4\,i_f+1}-1}\right) \end{equation}\] Since in weak inversion \(i_f \ll 1\), \(\sqrt{4\,\alpha\,i_f+1}-1 \cong 2\,\alpha\,i_f\) and \(\sqrt{4\,i_f+1}-1 \cong 2\,i_f\) and hence \[\begin{equation} v_{dssat,wi} \cong -\ln(\alpha) \end{equation}\] or \[\begin{equation} \alpha \cong e^{-v_{dssat,wi}}. \end{equation}\] For the usual value of \(v_{dssat,wi} = 4\), the ratio \(\alpha =\) 1.83e-02, which is equal to the value of \(r=q_d/q_s\) used above simply because in weak inversion \(q_d \cong i_r\) and \(q_s \cong i_f\).
Although the ratio \(r=q_d/q_d\) is not very intuitive a priori, it can however be interpreted from a circuit perspective. Indeed, recalling that \(q_s=g_{ms}\) and \(q_d=g_{md}\), the \(r=q_d/q_d\) ratio actually corresponds to the ratio of the drain to the source transconductance \[\begin{equation} r \triangleq \frac{q_d}{q_s} = \frac{g_{md}}{g_{ms}}. \end{equation}\] In the next section, we will show that the ratio \(1/r=g_{ms}/g_{md}\) is actually the voltage gain of a common-gate stage.
3 Interpretation of the \(q_d/q_s\) ratio
The circuit of Figure 5 represents a common-gate stage biased at a constant current \(I_b\) as can be found in a cascode gain stage. If we assume that the current source is ideal and we neglect the output conductance of the transistor, we get the small-signal circuit shown in Figure 6.
Since the drain current is maintained constant there can be no change in the drain current leading to [6] [7] \[\begin{equation} \Delta I_D = G_{md}\cdot \Delta V_D - G_{ms} \cdot \Delta V_S = 0. \end{equation}\] The voltage gain from the source to the drain is therefore given by [6] [7] \[\begin{equation} A \triangleq \frac{\Delta V_D}{\Delta V_S} = \frac{G_{ms}}{G_{md}} = \frac{g_{ms}}{g_{md}} =\frac{1}{r}. \end{equation}\] This voltage gain actually corresponds to the inverse of the factor \(r\) defined in the previous Section.
We can then rewrite the saturation voltage \(\eqref{eqn:vdssat_r}\) in terms of the voltage gain \(A\) as [6] [7] \[\begin{equation}\label{eqn:vdssat_a} v_{dssat} = 2 q_s\,\left(1-\frac{1}{A}\right)+\ln(A). \end{equation}\] Equation \(\eqref{eqn:vdssat_a}\) is plotted versus the inversion factor \(IC\) in Figure 7 for various values of \(A\).
We call also express the drain-to-source saturation voltage in terms of its value in weak inversion \(v_{dssatwi}\) \[\begin{equation}\label{eqn:vdssat_vdssatwi} v_{dssat} = 2 q_s\,\left(1-e^{-v_{dssatwi}}\right)+v_{dssatwi}. \end{equation}\]
The dashed black curves correspond to the weak and strong inversion asymptotes for \(v_{dssat,wi} =\) 4 \(U_T\), which corresponds to a voltage gain \(A =\) 54.60. Therefore a simple approximation of the saturation voltage valid from weak to strong inversion is given by \[\begin{equation}\label{eqn:vdssat_approx} v_{dssat} = 2 q_s\,\left(1-e^{-4}\right)+4 \cong \sqrt{4 IC+1} + 3 \end{equation}\] The approximation \(\eqref{eqn:vdssat_approx}\) is compared to \(\eqref{eqn:vdssat_vdssatwi}\) for \(v_{dssat,wi} =\) 4 in Figure 9. We see an almost perfect fit.
4 References
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[4]
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[5]
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[6]
V. C. Vincence, C. G. Montoro, and M. C. Schneider, “A high-swing MOS cascode bias circuit for operation at any current level,” in Proc. of the 2000 IEEE International Symposium on Circuits and Systems (ISCAS), 2000, pp. 489–492, vol. 5. doi: 10.1109/ISCAS.2000.857478.
[7]
V. C. Vincence, C. Galup-Montoro, and M. Cherem Schneider, “A high-swing MOS cascode bias circuit,” IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing, vol. 47, no. 11, pp. 1325–1328, 2000, doi: 10.1109/82.885143.